As I suspected earlier, vr-zone.com is reporting that RV770 consists of five clusters with 160 stream processors each (grouped in the same 4 IEEE754 +1 fashion as in the Rv6xx/R6xx cores).
My take: 5 slightly modified HD3650's (40 stream processors more than the 120 of the RV635), striped of their individual memory controllers altogether (which, as we saw with the RV670, RV610/20 and RV630/35, does impact the transistor count significantly), which would then access an on-die, but "off-array" common memory controller, bypassing the frame-buffer multiplication of the same data, a limitation of multi-chip rendering.
The connection between these "arrays" themselves and/or the common memory controller could be made by some form of on-chip coherent HyperTransport link.
Let's wait a bit more and see if i was way too off the mark or not...
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